The Android operating system, on the other hand, was designed from the start to support mobile devices and has proved that it can serve more than mobile phones. Using the Android OS for embedded in-vehicle entertainment provides all the entertainment features offered by a top-of-the-range, in-dash infotainment system with the addition of informative, driver-assisting content including hands-free calling, multimedia center, and a navigation system/Google maps. For an embedded open source expandable system (whereby the framework can be extended and applications can be developed for it), the Android OS can be enhanced to support multiple audio and video feeds. For example, IVI audio requirements include music, phone calls, sensor warnings, and navigation announcements, which must be managed and prioritized. Managing multiple displays, with an information-focus for the driver and entertainment-focus for passengers, is also a requirement. The UI for the driver should be arranged to minimize distraction, while passengers will want as much content as possible from their UIs. But many automotive OEMs and developers ask, “Why not just use the Android smartphone and tie it into a vehicle’s dash?” Not only would this be more cost effective for the developer, but the user would have instant familiarity with the system.
ACROSSER has provided innovative Embedded Computer solutions and quality products to over thousands customers on helping them reduce the time-to-market to gain the higher competence and to win the market.
In response to growing pressure to boost the performance and trim down the size of embedded applications,standards organizations meet regularly to optimize their portfolios in light of the latest available technology. These updated standards take advantage of new silicon architecture combining multiple processors, graphics elements, and complex I/O to deliver the next generation of preengineered, off-the-shelf modules to support many of the high-performance requirements of embedded product development.
IT managers are under increasing pressure to boost network capacity and performance to cope with the data deluge. Networking systems are under a similar form of stress with their performance degrading as new capabilities are added in software. The solution to both needs is next-generation System-on-Chip (SoC) communications processors that combine multiple cores with multiple hardware acceleration engines.
vGeneric multicore processors have been promoted as the solution to networking communication processing. In reality, they can’t address the scalability, determinism, and ease of programming required for next-generation networking infrastructure. An asymmetric multicore approach that blends multicore processors with networking-optimized accelerator engines and C-programmable libraries meets the challenges of next-generation networks.
Achieving deterministic performance is a key requirement for network operators to ensure reliability across wide variations of traffic profiles and applications. Multicore processors can meet performance challenges when running an application on a single, dual-core, or quad-core processor. However, when scaling to eight cores or beyond, performance scaling usually degrades. There are cases where eight cores deliver no better performance than four, and 16 cores actually run slower than eight.
Networking applications tend to be data-intensive, and generic multicore processors are highly susceptible to the impacts of memory latency on performance. The nonlinearities of memory latency (Figure 1) with regard to memory load combined with the nonlinearities of processor performance relative to memory latency can lead to unpredictable and unreliable performance. The innovative approach taken by LSI to solving this problem is asymmetrical multicore processors, which combine general-purpose processors with specialized accelerators for particular data-intensive tasks, resulting in an optimal, scalable solution.
Asymmetrical multicore processors improve performance predictability by combining general-purpose processors and accelerators to address the nonlinearities of memory latency.
Networking infrastructure applications tend to involve complex processing, intense memory utilization, and real-time, deterministic requirements. Asymmetric architectures address these challenges by seamlessly allocating the work between general-purpose multicore processors and specialized acceleration engines. These accelerators are specifically designed to tolerate memory latencies and perform predictably. This approach also enables the application to be built using fewer general-purpose multicore processors with far fewer lines of code. The asymmetric approach simplifies scaling challenges and delivers more deterministic performance at lower cost and power.
Networking applications demand a flexible approach to OSs. This flexibility is required not only to meet application requirements, but also to support the smooth migration of OEM legacy software and give designers the ability to choose the right OS for a particular application. It is important to simultaneously support multiple OSs on different cores without introducing overhead. At LSI, our hardware and software has been architected from the ground up with all this in mind, providing flexible support for the range of OSs used in networking applications.
Software tools such as compilers, simulators, and debuggers are required to support these processors. Simulators must be fast, support real-world throughput and traffic types, and perform accurately for software debugging. Ideally, tools are integrated to enable end-to-end software development in a single environment.
LSI has developed an integrated software development environment through six generations of communications processors. These tools have been hardened through many years of real-world deployment. LSI provides an Advanced Development Kit (ADK) consisting of highly scalable, customer-extensible modules that can be combined to enable quick and easy application development. These function-specific modules seamlessly enable rapid development of applications leveraging the asymmetric multicore architecture for wireless, wireline, and enterprise networking.
The ever-increasing performance demands of next-generation networks and applications, coupled with user expectations of reliability and quality of service, require purpose-built asymmetric multicore architectures to achieve wire-speed, deterministic performance at the lowest power and cost. LSI solutions for networking infrastructure applications are optimized with the right combination of multicore processors and accelerators to deliver scalable, reliable, and deterministic performance. We call this “Multicore Done Right.”
Although embedded devices destined for industrial applications have a wide range of design requirements due to the diverse environments in which they are deployed, almost all systems need some form of wired or wireless communications capabilities. Stand-alone industrial embedded devices are relatively rare, as users now demand remote access for data collection, management, maintenance, troubleshooting, software updates, and system security. For example, businesses need to monitor and collect real-time operational or throughput statistics from individual devices to evaluate the performance of manufacturing systems and methods.
Complex embedded systems can automatically run maintenance and diagnostic routines to evaluate reductions in performance and remotely schedule hardware updates. Many remote systems also require some type of security or surveillance features to detect and possibly prevent physical or virtual attacks. The challenge for embedded designers is to find the right communications technologythat delivers reliable, high-performance connectivity in an industrial environment with possible noise, extended temperatures, shock/vibration, and interference.
In this issue of Industrial Embedded Systems, we asked contributors to take a look at the principal issues and trends affecting contemporary embedded design for industrial applications and found that connectivity was a major topic in most of the articles and interviews. For example, in the Computing section, Mike Holt of Semitech Semiconductor illustrates techniques to optimize power line communications for Machine-to-Machine (M2M) applications such as automatic meter reading or control and management of streetlights, vending machines, or solar panels. In the same section, Lantronix VP of engineering Daryl Miller offers suggestions for making smart grids smarter by integrating M2M communications features into legacy equipment to enable remote access, control, and troubleshooting capabilities. Andreas Johannsen of Vincotech describes another important design requirement for industrial equipment, especially systems that operate 24 hours a day: power efficiency. Andreas shows how electronic commutated motor drives contained in an integrated power module can be up to 90 percent more efficient than conventional motor drives in industrial applications.
In the Networking/Sensing section, connectivity is a central theme in discussions on applications ranging from building automation to smart parking technology. In a Q&A session, HomePlug Powerline Alliance President Rob Ranck explains the current state of broadband networking over existing AC wiring within the home and outlines new standards that support smart gridapplications, electric vehicle charging stations, and HD streaming for movies or gaming. In a technical article targeting Building Automation Systems (BAS), Louis-Nicolas Hamer, VP at SCL Elements, describes the industry’s slow progress due to poor interoperability among multiple automation protocols and highlights a new All-in-One embedded gateway controller that can solve this BAS divergence. Citing unprecedented grown in the M2M industry, Mike Ueland, VP and general manager at Telit Wireless Solutions North America, shows how companies are deploying remote monitoring to increase efficiency and cut costs in managing industrial assets and systems. And finally, in a completely different connectivity application, Alicia Asín of Libelium offers a unique solution for automobile parking management that could potentially eliminate billions of hours of lost productivity along with billions of gallons of wasted fuel due to motorists cruising around searching for parking spaces.
This issue also includes our annual Resource Guide with a large number of embedded products divided into dozens of categories to simplify your next industrial design project. You’ll find a wide selection of off-the-shelf industrial systems, small form factor modules, power sources, panel computers, enclosures, and specialized embedded components to solve your unique requirements. You’ll also find embedded support software including operating systems plus data acquisition andmotion control systems. Our aim is to provide a reference source of available products that match your future design projects. If you have suggestions or products for the next Resource Guide, please let us know.
The articles and interviews in this issue include an extensive look at the embedded industry from the industrial viewpoint and should serve as a valuable technical reference for your next design project. In addition to the topic of connectivity, you can gain a wide-ranging perspective on multiple industrial design issues from diverse vertical market areas. Our plan is to continually search the embedded community to deliver guidelines and techniques to keep you on the leading edge and ahead of your competition. Please give us your ideas on print technical articles and online updates that we can provide to support your design efforts.
Understanding and selecting analog IP can be risky, but engineers today have more choices and more control than they think. Knowing how to manage the IP selection process can help engineers effectively meet objectives and reduce risk.
Analog IP landscape
The analog IP market has exploded in the past 10 years. Demand for ADC, DAC, Phase-Locked Loop (PLL), and DC-DC converter IP is expected to grow at more than 17 percent through 2015, according to Semico. Two forces are largely responsible for this. First, the amount of analog talent in the labor pool has reduced dramatically. Second, competitive pressures are putting premiums on time to market and costs. IP is seen as an effective strategy for meeting time to market and addressing significant bottleneck issues because it allows engineers to purchase blocks and amortize the cost over multiple projects.
Strategy + business model
Analog IP firms invest heavily in R&D to lead on the performance front and then market those products for a variety of applications. The model works great for innovation and for customers needing state-of-the-art performance. Performance premiums are often not necessary for the application. This is where proper requirements definition comes in handy.
Most analog IP firms charge upfront license, per-unit royalty, and related maintenance and service fees. Licenses can usually be expanded from single use to multisite to amortize costs more efficiently (see Figure 1).
Industrial computer, gaming platform, Embedded pc
Figure 1: An analog IP business model allows engineers to purchase blocks and amortize the cost over multiple projects.
Analog IP challenges
Because analog IP blocks are usually delivered as hard macros, they are largely dependent on process technology and are difficult to modify and test. This decreases the number of options and can make a customer more reliant on a specific foundry. Analog IP companies are exerting a great deal of effort to migrate their portfolios to smaller technologies, but are seeing major challenges at 40 nm and below. This has long-term implications for product roadmaps as costs grow exponentially at smaller technologies. These challenges present strategic trade-offs for embedded teams.
When ADC, DAC, or DC-DC controller IP is developed in all-digital RTL, many of these challenges are removed. All-digital ADC cores, for instance, are easily modified for special requirements, technology independent, FPGA embeddable, and digitally testable. These cores are often smaller and lower power due to the use of a digital fabric. The drawback of this approach is limited resolution and bandwidth. At Stellamar, ADCs currently offer up to 16-bit resolution and 400 kHz bandwidth. By comparison, analog ADCs offered in mixed-signal FPGA packages provide 12 bits and 500 kHz bandwidth.
Steps to evaluate IP/system fit
With a high-level understanding of the analog IP landscape, engineers can concentrate on avoiding the two most common problems when selecting IP: unclear objectives and improper requirements definition. To do this, a team considering buying IP must thoroughly understand these two dynamics.
Project objectives
Given the trade-off of offering smaller technologies at higher costs, clarity on the most important overall project objectives is critical. Analog IP is one tool of many that can help engineers meet an objective, and whatever tool is chosen dictates how the team allocates resources to meet the objective.
One of the best tools for prioritizing objectives is the CARVER matrix that Navy SEALs use to assess the value of a military target in a quick, no-fail way. This exercise can shed light on the most important issues to the design team, including reuse versus custom, foundry reliance, and technology portability and prototyping. Try this exercise in a group or individually to compare how team members view objectives.
First, list critical objectives for the embedded design project. Be specific. Objectives such as low power and small area aren’t nearly as effective as actual numbers. Objectives should also include higher-level strategies such as “foundry neutral” or “ensures process roadmap.”
Next, score the objectives 1-5 (5 being highest) on each of six criteria:
Criticality: How critical is this objective?
Accessibility: How achievable is the objective with internal resources? Purchased IP?
Recognizability: Does the team recognize the objective as important?
Vulnerability: What force is needed to achieve the objective? Can it be achieved in a certain time frame? Are large amounts of resources needed?
Effect on mission: How much closer does this objective get the design to meeting the overall strategy?
Return on effort (ROI): How much bang for my buck?
Table 1 shows an example CARVER matrix.
Industrial computer, gaming platform, Embedded pc
Table 1: A CARVER analysis can shed light on an IP project by rating the importance of design objectives according to six critical factors.
In this example, the team’s overall strategic objectives are to limit reliance on one foundry and ensure the IP can get the product to 22 nm. These objectives are achievable in the current IP landscape if technical requirements can be met, leading to the next dynamic of understanding.
Technical requirements
In the old days of in-house IP development, engineers would gather requirements and build IP blocks exactly according to those specs. This often increased cost, lead times, and risk when targeting a new technology. As cost and time-to-market pressures have transferred IP production to the “outhouse,” adherence to specifications has relaxed. This benefits IP companies who market their higher-performance blocks for wide-ranging, lower-performance applications.
A vendor has limited ability to meet specific requirements in a given budget or time frame. Foundry and process portability challenges further limit optimal choices for the customer. These limits have ramifications from higher power consumption to price premiums for unnecessary performance. Proper requirements definition is key to understanding where trade-offs will occur and how those trade-offs can be counterbalanced.
To start proper requirements definition, some key questions need to be asked, including:
What is being measured, and what is needed?
What are the minimum resolution and bandwidth needed to completely convert the input?
What are the power and size budgets?
What are the input characteristics?
Are there unique timing needs?
Is the prototype system FPGA-based?
How can the design convert from FPGA to ASIC?
What foundry created the IP? What process was used?
What are the test requirements?
Standards exist for many functions. For instance, audio is still 12 bits and 15 kHz bandwidth. Professional audio is higher, and knowing this difference can save money and time. As another example, many DC-type measurements have very small bandwidth, often sub-10 Hz, yet engineers often choose ADC IP with greater than 1 MHz bandwidth because of availability. This is like using a sledgehammer to drive the head of a pin. It gets the job done, but will consume more power than necessary. Similarly, integral and differential nonlinearity degrades the effective number of bits for some ADCs. If the requirement is 12 bits, a 14-bit ADC block might be needed to achieve the required 12-bit resolution.
IP selection
Armed with prioritized strategic objectives and exact technical requirements, the team can start the selection process. Websites such as Chipestimate.com and Design-reuse.com are good places to start. Xilinx and Microsemi also provide robust IP ecosystems that include analog IP functions from providers like Stellamar.
To attain the level of comfort needed to make a selection, the team must ask the vendor a number of questions, including:
Does the vendor have customers and success stories?
Are the cores silicon-proven?
What level of support is provided?
Can the core be evaluated before purchase?
What deliverables are provided?
What is the licensing structure?
How long will it take to tailor IP to specific needs?
How long has the company been providing IP cores?
How free is the company with sharing basic information?
What strategic partnerships does the vendor have?
By following this roadmap in sequence and asking all of the important questions, the design team should be confident that third-party analog IP selection and integration can help meet strategic objectives and add significant value to the overall system design.
The embedded world Exhibition&Conference is the world’s biggest exhibition of its kind and the meeting-place of the international embedded community. Embedded technologies are in action everywhere – whether in the car, data and telecommunication systems, industrial and consumer electronics, military systems or aerospace.
Industrial computer, gaming platform, Embedded pc
This event sets standards and records every year – now for the eleventh time in 2013. Exhibitors from all over the world present the entire spectrum of embedded systems: hardware, software, tools and services. “The embedded world Exhibition&Conference is growing continuously and rapidly in the same way that the embedded sector is gaining in importance – the embedded community can look forward to a record event,” says Alexander Mattausch, Exhibition Manager of embedded world.
The Intel® Core™2 Quad processor for desktop PCs is designed to handle massive compute and visualization workloads enabled by powerful multi-core technology.
Providing the bandwidth you need for multi-threaded applications, Intel Core 2 Quad processors are built on 45nm Intel® Core™ microarchitecture enabling, faster, cooler, and quieter desktop PC and workstation experiences.
Intel® Wide Dynamic Execution, enabling delivery of more instructions per clock cycle to improve execution time and energy efficiency
Intel® Intelligent Power Capability, designed to deliver more energy-efficient performance
Intel® Smart Memory Access, improving system performance by optimizing the use of the available data bandwidth
Intel® Advanced Smart Cache, optimized for multi-core processors, providing a higher-performance, more efficient cache subsystem
Intel® Advanced Digital Media Boost, accelerating a broad range of multimedia, encryption, scientific and financial applications by significantly improving performance when executing Intel® Streaming SIMD Extension (SSE/SSE2/SSE3) instructions
Intel® HD Boost³, with Intel® Streaming SIMD Extension 4 (Intel SSE4) instructions for even greater multimedia performance and faster high definition video editing and encoding
The AMB-QM77T1 is the newest Mini-ITX industrial mainboard from acrosser Technology that supports both of the 3rd and 2nd generation Intel Core i7/i5/i3 mobile processor by Intel QM77 chipset and FCPGA 988 socket.
acrosser Technology Co. Ltd, global professional industrial and embedded computer provider, announces the new Mini-ITX mainboard, AMB-D255T1, which carries the Intel dual- core 1.86GHz Atom Processor D2550.
．Intel Atom D2550 1.86GHz
．1 x DDR3 SO-DIMM up to 4GB
．1 x VGA
．1 x HDMI
．1 x 24-bit LVDS
．6 x USB2.0
．4 x COM
．1 x GbE (Realtek RTL8105E)
．1 x PS/2 KB/MS
．1 x MiniPCIe slot
．1 x SATA with power connector
．8-bit GPIO
